The present invention generally relates to multi-port time switch elements, and more particularly to a multi-port time switch element for use in a transmission equipment having a cross-connect function.
Recently, transmission equipments do not simply make a multiplexing, but also have the so-called cross-connect function which outputs a multiplexed signal to an arbitrary port in predetermined units. A time switch is popularly used to realize this cross-connect function.
Conventionally, the cross-connecting of eight channels of data, for example, is carried out as follows. That is, channels data CH1, CH2, CH3, . . . shown in FIG. 1A are successively written into a memory MEM shown in FIG. 1B at addresses (ADD) 0, 1, 2, . . . in this sequence. The data are read out from the memory MEM in a desired sequence, that is, from the addresses 1, 3, 0, 7, 4, . . . , for example. As a result, a data sequence CH2, CH4, CH1, CH8, CH5, . . . is obtained, thereby completing the cross-connecting.
FIGS. 1A and 1C show multiplexed data, and the data CH1, CH2, . . . are obtained time-sequentially in this sequence in FIG.1A while the data CH2, CH4, . . . are obtained time-sequentially in this sequence in FIG. 1C. FIGS. 1A and 1C show the data at each port, and if there are eight input/output ports, for example, CH1, CH2, . . . respectively correspond to the data at input/output ports 1, 2, . . . .
If the data of eight channels are multiplexed at one input/output port, the cross-connecting may be carried out as shown in FIGS.1A through 1C. However, when there are many input/output ports, the required memory capacity increases. The increase in the memory capacity results in the increase in the number of memories which are required, meaning an increase in hardware as will be described hereafter.
FIG. 2 shows an example where there are three input/output ports. In this example, data 1 and 2, data 3 and 4, and data 5 and 6 received at the three input ports IP1, IP2 and IP3 are cross-connected to data 3 and 6, data 4 and 1, and data 5 and 2 at the three output ports OP1, OP2 and OP3.
If only a single memory MEM1 were used for this cross-connecting, the data 1, 3 and 5 and the data 2, 4 and 6 would be written into the memory MEM1 in the received sequence according to the order of the input ports IP1 through IP3 which is from the top to bottom in FIG. 2. The data 3, 4 and 5 and the data 6, 1 and 2 would be read out from the memory MEM1 in this sequence to be output to a desired port via a selector (not shown). However, when only one memory MEM1 is used, the data 1, 3 and 5 are written by specifying a write address i, and the data 2, 4 and 6 are written by specifying a write address j. In addition, the data 1, 3 and 5 are read from the memory MEM1 by specifying a read address i and the data 2, 4 and 6 are read by specifying a read address j. In other words, the write and read addresses for the data 1, 3 and 5 are the same, and the write and read addresses for the data 2, 4 and 6 are the same. For this reason, although the data 3 and 5 can be read out from the memory MEM1 simultaneously, the data 4 cannot be read out at the same time as the data 3 and 5 because the data 4 is written at an address which is different from the addresses where the data 3 and 5 are written. Similarly, the data 1 cannot be read out at the same time as the data 2 and 6.
Therefore, if the combination of the input data and the output data are to be freely selected, it becomes necessary to provide three memories MEM1 through MEM3 in correspondence with the three output ports OP1 through OP3 with respect to one input port, and thus, nine (3.times.3) memories are required with respect to three input ports IP1 through IP3. By providing nine memories, the data 1 and 2 received at the input port IP1 can be written into three memories in the received sequence and read out in an arbitrary sequence to be output to a desired output port. The data 3 and 4 received at the input port IP2 and the data 5 and 6 received at the input port IP3 are respectively written into three memories in a similar manner and output to desired output ports. Accordingly, the data received at the input ports IP1 through IP3 can be output to the desired ones of the output ports OP1 through OP3 in an arbitrary sequence or combination.
Of course, if the memory can carry out the write and read operations at a high speed, it is possible to cross-connect the data received at the multi-channel input ports to the output ports without using as many memories as described above. However, when the data received at the input ports are transmitted at a high speed, the memories must carry out the write and read operations at a speed higher than transmission speed of the received data, and it is difficult to find memories which can operate at sufficiently high speeds.
According to the conventional time switch element, only one word of data can be read at one time out of the data which are written in the memory. For this reason, when the data quantity is large, a large number of memories must be used depending on the number of ports. In other words, even if all of the data are written into one memory, the data cannot be read out simultaneously, and thus, a plurality of memories are used instead. The same data contents are written into these memories and used depending on the output ports used. Consequently, the hardware increases depending on the data quantity to be processed and the number of ports used.